国际测试会议论文集

This paper consists of the following sections. In section 2, a review of the design implementation is given. Section 3 describes the test setup and the test plan while section 4 shows the measured results from the fabricated chips. Section 5 compares the design measurements with measurements by Wavecrest equipment while section 6 discusses limitations of this design. Section 7 shows possible design improvements, section 8 compares these results with previous works,

and section 9 summarizes the key features. Conclusions are drawn in section 10.

2. Design implementation

This design was created from theoretical ideas and analysis. Appropriate device sizes and robust design were determined through simulation using HSPICE. The design implementation and the simulation results follow.

2.1 Theoretical design

The time-to-digital conversion (TDC) implemented in this design converts an input clock period to a voltage, which is then digitized. The digitized value represents the measured clock period. Period jitter can be extracted from the difference between the expected value and the measured value. Statistical post-processing can be performed on this measured data for other jitter extraction. The method permits the measurement of accumulated jitter over N periods, where N is selectable (N=8, 10, 16, and 18). This capability allows jitter sampling over many cycles, potentially useful to study jitter as function of time.

The period-to-voltage converter uses a simple charge pump to charge the gate capacitance of the input comparators of the ADC. The comparators are all-digital (as opposed to the conventional analog comparators) and use inverter chains to set the reference levels for comparisons. The inverter chains are designed with different switching thresholds. Each threshold voltage represents the reference voltage of that comparator. Each chain is a cascade of 3 stages, each stage composed of parallel inverters: the first stage has 8, the second has 4, and the last has 2 parallel inverters. This topology makes the design more robust with respect to process variation [8]. The inverter

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thresholds (reference levels) were separated by 35 mV,

determined through analysis to make sure that neighboring chains were unlikely to switch out of

sequence due to process variations. Bubble correction logic eliminates any overlap in the output of the comparators due to process variation and device mismatch. A regular flash encoder provides the final digital output.

Figure 2 illustrates this method for period jitter measurement. The top plot shows the clock input converted into the charge control signal. The middle plot shows the charging of the ADC input capacitance (composed of gate capacitances of all input comparators). The bottom plot shows the histogram of the measured outputs for jitter extraction.

Figure 2: Proposed jitter measurement method.

The design was implemented in a 0.25-µm BiCMOS process, even though all the circuits are strictly CMOS. There are two additional test structures besides the complete design. The first test structure is used to check the reference level and the functionality of each comparator chain. The second test structure is a set of comparators designed with different reference levels separated by 16 mV, 8 mV and 4 mV. This structure determines whether a higher resolution can be implemented by decreasing the separation of the comparators’ reference levels.

Figure 3 shows the layout of the entire design: section A is the jitter measurement circuit, section B is one complete comparator, and section C is the set of test comparators previously described.