Technology Decomposition for Low-Power Synthesis y

Technology Decomposition for Low-Power Synthesisy Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana, IL 61801@y Abstract where P (@x ) is the probability of the Boolean difference of y with respect to xi. Therefore, more judiTechnology decomposition and technology mapping cious choices for internal functional blocks based on (1) are two potential stages for minimizing circuit power will, by-design, give less active and lower-power cirduring logic synthesis. Since power in CMOS circuits cuits. This idea is the basis of our work on low-power is directly dependent on the extent of circuit switching synthesis. While it is important to attack the syntheactivity, we present a novel procedure to construct a sis problem at all levels, in this paper we focus on the low-activity circuit structure in the technology decomtechnology decomposition step and propose a new alposition stage. This would result in low-power circuits gorithm that achieves lower power circuits on a variety when mapped. The algorithm uses the transition denof test cases, with little area or delay penalty. sity as a measure of switching activity and is applicable to both synchronous and asynchronous static circuits. 2. Background Our results show power reductions of up to 48% (on Consider a synchronous sequential circuit. Asaverage 10%), with little area or delay penalty. suming edge-triggering, the latches draw power in syn1. Introduction chrony with the clock, updating the inputs to the comThe high device counts and clock frequencies of binational blocks. Despite the synchronous switching modern ICs has made power dissipation of VLSI chips of the inputs to the combinational blocks, the internal a major consideration during chip design. Hence the gates may make several transitions before settling to need for low-power logic synthesis CAD tools to aid in their steady state values for that clock period. the design process. These additional transitions, called hazards or In the popular CMOS and BiCMOS technologies, glitches, can cause as high as 70% of the total power 2]. logic gates draw power only during logic transitions, The extent of glitching depends on (1) the mode of so that the power-dissipation depends on the switching switching of inputs (synchronous or asynchronous) and activity inside the circuit. This complicates the low(2) the racing of the signals arriving at a gate. Hence, power synthesis problem, since the exact input signals for a low-power technology decomposition procedure are generally unknown during the design phase. Furto yield best results, it should address these challengthermore, it is practically impossible to estimate the ing aspects of design, viz., handling glitches and allowpower by simulating the circuit for all possible inputs. ing for both synchronous and asynchronous operations. This input pattern-dependence problem can be Previous work in this area makes use of signal solved by using probabilities to describe the set of

all probability (average fraction of clock cycles in which possible logic signals. Speci cally, we will use a meathe steady state value of the node is a logic high) and sure of switching activity, called the transition dentransition probability (average fraction of clock cycles sity 1], that can be e ciently evaluated without rein which the steady state value of the node is di erquiring exact information about the primary input sigent from its initial value). Both these measures are nals. The transition density at a node x in the circuit una ected by the circuit internal delays and make the is the average number of logic transitions per second implicit assumption that the switching is synchronous at that node, denoted by D(x). As part of this forfor all the gates, so that glitching is not accounted for. mulation, it is found 1] that the density D(x) is diAnother aspect of this problem that usually rerectly related, through a simple linear expression, to quires approximations is the signal independence isthe Boolean function at node x, as follows: sue. In practice, the signals inside a circuit may be n correlated so that, for instance, two nodes may never X@y D(xi ) (1) P D(y)= be simultaneously high. It is computationally too ex@xi i=1 pensive to compute these correlations. So the circuit nodes are usually assumed to be independent. We refer to this as a spatial independence assumption. Any This work was supported by the National Science other independence issue is whether the values of the Foundation (NSF) under grant MIP{9308426. i

Rajendran Panda and Farid N. Najm

IEEE Custom Integrated Circuits Conference, 1995.