元器件交易网www.1mpi.com

Preliminary

GS8640Z18/36T-xxxV

100-Pin TQFPCommercial TempIndustrial TempFeatures

NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM , NoBL and ZBT SRAMs

1.8 V or 2.5 V core power supply 1.8 V or 2.5 V I/O supply

User-configurable Pipeline and Flow Through mode Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices Byte write operation (9-bit Bytes)

3 chip enable signals for easy depth expansion ZZ Pin for automatic power-down

JEDEC-standard 100-lead TQFP package

RoHS-compliant 100-lead TQFP package available

72Mb Pipelined and Flow Through

Synchronous NBT SRAM250 MHz–167 MHz 1.8 V or 2.5 V VDD1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS8640Z18/36T-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

The GS8640Z18/36T-xxxV is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 100-pin TQFP package. -2504.04106.5280

-2005.03507.5250

-1676.03058.0240

UnitnsmAnsmA

Functional Description

The GS8640Z18/36T-xxxV is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Parameter Synopsis

KQtCycle(x18)Curr (x32/x36)

KQtCycle(x18)Curr (x32/x36)

Pipeline3-1-1-1

Flow Through2-1-1-1