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Experimental Results for High-Speed Jitter Measurement Technique

Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry Lin, Mani Soma,

Hosam Haggag2, Jeff Huard3, Jim Braatz3

Department of Electrical Engineering, University of Washington, Seattle, WA

2

Santa Clara Design Center, National Semiconductor, Santa Clara, CA 3

Tacoma Design Center, National Semiconductor, Federal Way, WA

Abstract

A BIST method to measure jitter without external references is presented. Measured data from 0.25-µm BiCMOS chips show jitter resolution about 30 to 50 ps over 8 cycles of a 1 GHz input signal.

VDL was solved by component-invariant VDL, at the expense of test time [6]. These techniques can be easily integrated for on-chip test. However, these two techniques require a jitter-free reference clock. As a result, these methods require careful design consideration to minimize jitter in the reference signal.

In past approaches, TDC architecture was comprised of a time-to-amplitude converter followed by an ADC [7]. Two voltages are pre-charged to a fixed value and discharged over a measured time. The voltage difference is converted into the time domain. This method requires an off-chip solution for the capacitor, uses a reference voltage for the ADC and is implemented using emitter coupled logic (ECL). Integration using this technique for BIST is difficult in CMOS IC technology.

Other implementations [10] use peak detectors and comparators to measure time. The peak detectors are used to minimize the stored data while a time-to-amplitude converter acquires the timing information until an ADC can digitize the value. A final solution in [9] uses delay lines and an interpolator to improve the measurement accuracy. Counters count the gate delay and the periods to provide a time measurement.

The design for our measurement technique was presented in [8], and the purpose of this paper is to present the test results. The technique uses the clock signal under test to control the charging of the input capacitance of an ADC. The charged voltage is a function of the clock period, and the ADC converts this voltage to a digital measure of the clock period, from which jitter can be extracted. This method measures accumulated jitter over N clock cycles, where N is a selectable value. One advantage of this design is that it does not require an external jitter-free reference clock or a voltage reference. Figure 1 shows the design architecture [8].

1. Introduction

Data communication systems and microprocessor speeds are moving into the GHz range. With the increase in data rates, it is becoming more difficult to meet the timing requirements, and system designers require more accurate jitter measurement techniques. The cost of jitter measurement is high using Automated Test Equipment (ATE) for GHz clocks, and built-in self test (BIST) is an option to consider. A successful BIST design must possess the following characteristics:

1. Functionality at GHz frequencies

2. Quick measurement (<1 ms/5000 samples) 3. High Resolution (<10 ps)

4. Immunity to noise and mismatch 5. Digital components

6. Minimal inputs and outputs 7. Minimized area

There are many designs to convert time to a digital value or to measure jitter. One recent external technique measures jitter by digitizing signal samples [1] while another one uses statistical analysis combined with undersampling [2]. The digitization method in [1] applies a sine wave to an analog-to-digital converter (ADC) and uses the signal under test as the ADC clock. With the undersampling technique [2], the test signal is sampled by an ATE in incremental time shifts near an edge transition and stored to create a statistical picture.

Examples of popular on-chip implementations of time-to-digital converters (TDC) are the delay lock loop (DLL) and the vernier delay line (VDL). The DLL measures the phase difference between a series of delay elements and the signal under test [3, 4]. The VDL extends DLL by measuring the differences between two gate delays [5]. Matching issues of delay elements in

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